1. Field of the Invention
The present invention relates to a thin film semiconductor apparatus and a production method thereof and, more particularly, to a thin film semiconductor apparatus having the structure suitable for high performance and large area and a production method of thin film semiconductor apparatus capable of producing it readily and at low cost.
2. Related Background Art
The large-area thin film semiconductor apparatus includes apparatus such as image reading apparatus or image display apparatus in which unit elements are arrayed one-dimensionally or two-dimensionally, and a thin film transistor is a device often used for driving of the apparatus and for reading or writing of information.
This thin film transistor will be first described. The structure of the thin film transistor is assumed to be of the general inverse stagger type. FIGS. 1A-1D, which are illustrated as schematic cross-sectional views, show an example of the structure of the thin film transistor and an example of steps of a production method thereof.
Using a material such as aluminum or chromium, a first conductive layer 602 is deposited on substrate 601 such as a glass substrate by vapor deposition or sputtering (FIG. 1A). This layer is then patterned in a desired shape by photolithography. This forms gate electrode 603 of thin film transistor (FIG. 1B).
Then a gate insulating layer, semiconductor layers, etc. will be deposited on this gate electrode, using the CVD process (Chemical Vapor Deposition) or the like. Specifically, a hydrogenated amorphous silicon nitride film is deposited as gate insulating film 604, using silane (SiH.sub.4) gas, ammonia (NH.sub.3) gas, and hydrogen (H.sub.2) gas. Subsequently, with silane gas and hydrogen gas, an intrinsic hydrogenated amorphous silicon layer is deposited as intrinsic semiconductor layer 605. Further, using silane gas, and phosphine (PH.sub.3) gas diluted with hydrogen gas, an N.sup.+ -type hydrogenated amorphous silicon layer is deposited as impurity semiconductor layer 606. Then a second conductive layer 607 is deposited using the material such as aluminum or chromium by vapor deposition or sputtering (FIG. 1C). Subsequently, it is patterned in a desired shape by photolithography. This is used as a metal layer for the source electrode and drain electrode of thin film transistor. Then an unnecessary portion of the N.sup.+ -type hydrogenated amorphous silicon layer is removed by dry etching to form ohmic layer to the source electrode and to the drain electrode, thus completing the source electrode and drain electrode 608, 609 (FIG. 1D).
Further, a two-dimensional image reading apparatus is exemplified as a thin film semiconductor apparatus which is a combination of such inverse stagger type thin film transistors with photoelectric conversion elements. FIG. 2A is a schematic plan view of one pixel in the image reading apparatus. FIG. 2B is a schematic, cross-sectional view along 2B--2B of FIG. 2A.
In FIGS. 2A and 2B, numeral 801 designates a substrate, 802 a lower electrode of photoelectric conversion element, 803 a gate electrode, 804 an insulating layer, 805 a semiconductor layer, 806 an ohmic layer (ohmic contact layer), 807 a drain electrode, 808 a source electrode, and 809 an insulating, protective layer. Further, S11 represents the photoelectric conversion element (an MIS type photosensor in this example), T11 the thin film transistor (TFT), SIG a signal line, g1 a gate driving line, and V.sub.1 a power source line. In FIG. 2A the insulating layer 804, ohmic layer 806, and protective layer 809 are not illustrated in order to avoid complexity of illustration, and the semiconductor layer 805 is illustrated by a solid line.
As illustrated, the photoelectric conversion element S11 has the structure in which the lower electrode 802, insulating layer 804, semiconductor layer 805, and ohmic layer 806 are stacked in the stated order on the substrate 801. The ohmic layer 806 has a function as an upper electrode of the photoelectric conversion element S11. The photoelectric conversion element S11 has the insulating layer 804 and semiconductor layer 805 between the ohmic layer 806 and the lower electrode 802 becoming the upper and lower electrodes, thereby composing the MIS type structure.
The thin film transistor has the gate electrode 803 on the substrate 801, and has the insulating layer 804 becoming a gate insulating film, and the semiconductor layer 805 in this order thereon. The ohmic layer 806 is formed on the semiconductor layer 805 with a space forming a channel region corresponding to the gate electrode 803, and through this ohmic layer 806 the transistor has a conductive material, for example a metal such as aluminum, as source and drain electrodes 808, 807.
The lower electrode 802 is formed so as to extend from the power source line V.sub.1, the gate electrode 803 from the gate driving line g1, and the drain electrode 807 from the signal line SIG, respectively.
In the drawing numeral 806 on the photoelectric conversion element S11, being the MIS type photosensor, is an N.sup.+ -type hydrogenated amorphous silicon layer and functions as a window layer. This N.sup.+ -type hydrogenated amorphous silicon layer also functions as an injection preventing layer (a blocking layer), as well as functioning as an electrode layer as described above.
FIG. 3 shows an equivalent circuit of one pixel of this image reading apparatus. One pixel has an MIS type photosensor S11 and a thin film transistor T11 for transmission of signal. Letters D, G indicate the upper electrode (the ohmic layer 806 in this example) and the lower electrode 802, respectively, of the MIS type photosensor. Symbols Cgs, Cgd represent capacitors formed by overlap between the gate electrode 803 and the source electrode 808 and overlap between the gate electrode 803 and the drain electrode 807 (d.sub.1, d.sub.2 in FIG. 1D) of the thin film transistor, and Vs stands for a power source. The charge created in the MIS type photosensor S11 by light is stored through the thin film transistor T11 in the capacitors Cgs, Cgd, and thereafter this charge is read out by a reading circuit not illustrated. This is a case of one bit, but, in practice, these Cgs, Cgd are added to those of the other thin film transistors connected to this gate line. In this way storage capacitors make use of Cgs, Cgd.
The thin film transistor and photoelectric conversion element both can be produced by the same layer-forming process and both have the MIS (Metal Insulator Semiconductor) type structure having the electrode on the lower side.
An example of drive of the above-stated MIS type photosensor will be described below, using the schematic energy band diagrams shown in FIG. 4A and FIG. 4B.
FIG. 4A is a schematic energy band diagram of the photoelectric conversion element to show the action in a refresh mode and FIG. 4B the action in a photoelectric conversion mode. In FIG. 4A numerals 1 to 5 correspond to the drain electrode 807, the ohmic layer 806, the semiconductor layer 805, the insulating layer 804 and the lower electrode 802, respectively. Accordingly, the diagrams show the states along the direction of the layer thickness. In the refresh mode the D electrode has a negative potential relative to the G electrode and, therefore, holes indicated by black dots in the intrinsic (intrinsic or substantially intrinsic) hydrogenated amorphous silicon layer 3, which is, for example, the semiconductor layer 805, are guided into the D electrode by an electric field. At the same time as it, electrons indicated by white circles are injected into the intrinsic hydrogenated amorphous silicon layer 3. At this time some holes and electrons are recombined in the N.sup.+ -type hydrogenated amorphous silicon layer 2, which is, for example, the ohmic layer 806, and in the intrinsic hydrogenated amorphous silicon layer 3 to annihilate. After a lapse of a sufficiently long period of time, the holes in the intrinsic hydrogenated amorphous silicon layer 3 will be swept out of the intrinsic hydrogenated amorphous silicon layer 3 (FIG. 4A). When the mode is switched from this state into the photoelectric conversion mode, the D electrode will be provided with a positive potential relative to the G electrode and, therefore, the electrons in the intrinsic hydrogenated amorphous silicon layer 3 are instantaneously guided into the D electrode. However, since the N.sup.+ -type hydrogenated amorphous silicon layer 2 acts as an injection preventing layer, holes are prevented from being injected from the D electrode into the intrinsic hydrogenated amorphous silicon layer 3. When in this state light is incident into the intrinsic hydrogenated amorphous silicon layer 3, the light is absorbed to create an electron-hole pair. This electron is guided into the D electrode by the electric field and the hole moves in the intrinsic hydrogenated amorphous silicon layer 3 to reach the interface to the hydrogenated amorphous silicon nitride film 4, which is, for example, the insulating layer 804. At this point the movement of the hole is blocked, so that the hole will remain in the intrinsic hydrogenated amorphous silicon layer 3. At this time the electron moves into the D electrode while the hole moves to the interface to the hydrogenated amorphous silicon nitride layer 4 in the intrinsic hydrogenated amorphous silicon layer 3. Therefore, an electric current flows from the G electrode in order to keep the electrical neutrality in the element. Since this electric current corresponds to the electron-hole pair created by the light, the electric current is proportional to the incident light.
FIG. 5 shows an example of a schematic circuit diagram of the whole of the image reading apparatus. Photoelectric conversion elements S11 to S33, thin film transistors T11 to T33 for driving, wirings, etc. are of the structure as described above, whereby they can be formed on the same substrate, using the layers formed by the same process. Vs represents a power source for reading and Vg a power source for refresh. Each power source Vs, Vg is connected through switch SWs, SWg to the lower electrodes G of the all photoelectric conversion elements S11 to S33. The switch SWs is connected through an inverter to a refresh control circuit RF while the switch SWg directly to the refresh control circuit RF. The switches are controlled in such a manner that the switch SWg is on during a refresh period and the switch SWs is on during the other periods. Signal outputs are connected to an integrated circuit for detection IC by signal lines SIG. In FIG. 5 nine pixels are arranged in three blocks, outputs of three pixels per block are transferred at one time, and the detection integrated circuit successively converts the signals into outputs to output them. Although this example shows the two-dimensional image input section of nine pixels for easier description, the image input section is practically constructed in the structure of higher density of pixels. For example, supposing the pixel size is 150 .mu.m square and the image reading apparatus is constructed in the size of 40 cm square, the number of pixels is approximately 1,800,000.
An example of production steps of the above image reading apparatus is shown in FIGS. 6A-6F.
1. On clean glass substrate 801 after cleaned, chromium is deposited in the thickness of 1000 .ANG. by sputtering. A pattern of photoresist is formed in a desired shape on this chromium layer. Etching is conducted with this photoresist pattern as a mask. After that, the photoresist is peeled off and the substrate is cleaned, thereby forming the gate electrodes 803 of thin film transistor of each pixel, lower electrodes 802 of MIS type photosensor, and wiring portions. (FIG. 6A)
2. On this substrate a hydrogenated amorphous silicon nitride layer to become the insulating layer 804 is then formed by the plasma enhanced CVD using silane (SiH.sub.4) gas, ammonia (NH.sub.3) gas, and hydrogen (H.sub.2) gas. Subsequently, an intrinsic hydrogenated amorphous silicon layer to become the semiconductor layer 805 is formed by the plasma enhanced CVD using silane (SiH.sub.4) gas and hydrogen (H.sub.2) gas. Further, an N.sup.+ -type hydrogenated amorphous silicon layer to become the ohmic layer 806 is formed by the plasma enhanced CVD using silane (SiH.sub.4) gas, phosphine (PH.sub.3) gas, and hydrogen (H.sub.2) gas. (FIG. 6B)
3. A photoresist pattern for contact holes and isolation is produced by photolithography and with this photoresist pattern as a mask dry etching is carried out to remove parts of the insulating layer 804 (hydrogenated amorphous silicon nitride layer), semiconductor layer 805 (intrinsic hydrogenated amorphous silicon layer), and ohmic layer 806 (N.sup.+ -type hydrogenated amorphous silicon layer). Then the photoresist is peeled off and the substrate is cleaned, thus achieving formation of contact holes (not illustrated) and isolation. (FIG. 6C)
4. Aluminum is deposited in the thickness of 1 .mu.m thereon by sputtering. After that, a photoresist pattern is formed in a desired shape on the aluminum layer. Using this photoresist pattern as a mask, etching is carried out. Then the photoresist is peeled off and the substrate is cleaned, thus obtaining the source electrodes 808 of thin film transistors, the drain electrodes 807 of thin film transistors, and electrodes of wiring portions. At this time the aluminum layer on the MIS type photosensor is removed, and in this example the N.sup.+ -type hydrogenated amorphous silicon layer being the ohmic layer 806 is utilized as a window layer and as upper electrodes. (FIG. 6D)
5. Subsequently, a photoresist pattern is formed in a desired shape on this aluminum pattern and with this pattern as a mask, etching is carried out of only the N.sup.+ -type hydrogenated amorphous silicon layer of the ohmic layer 806 in channel portions of thin film transistors corresponding to portions between the source electrodes 808 and the drain electrodes 807. Then the photoresist is peeled off and the substrate is cleaned, thus forming the channels. (FIG. 6E)
6. Subsequently, a hydrogenated amorphous silicon nitride layer is formed as the surface protective layer 809 in the thickness of 6000 .ANG. by the plasma enhanced CVD using silane (SiH.sub.4) gas, ammonia (NH.sub.3) gas, and hydrogen (H.sub.2) gas.
In the thin film transistor described above, the overlap widths d.sub.1, d.sub.2 of 2 to 3 .mu.m are necessary between the gate electrode 603 and the source or drain electrode 608, 609, as shown in FIG. 1D. This results from the limitation of accuracy of alignment in forming the photoresist pattern for the source and drain electrodes in the production method as described above. Namely, redundancy is given to alignment so that deviation of alignment will not degrade the function of TFT. In the portions of the overlap widths, however, the capacitor Cgs is formed between the gate electrode and the source electrode and the capacitor Cgd between the gate electrode and the drain electrode.
The capacitors Cgs, Cgd of thin film transistor sometimes cause various negative effects. For example, the capacitors delay the response of thin film transistor to the gate voltage. Specifically, when the charge of each pixel is read out, the voltage is successively applied to the gate electrodes of thin film transistors for transmission in the respective pixels to turn each gate on, thereby transferring the stored charge. The response to the gate voltage at this time is defined by resistance R of gate wiring and capacitances of the capacitors Cgs, Cgd. This sometimes raised the problem that the image reading apparatus failed to follow high-speed switching operation for operating the whole apparatus, for example, in a mode compatible with moving picture. The capacitors often have too large capacitances relative to signal amounts to be used as storage capacitors. Therefore, even a small output needs to be read out, and a very low noise IC is necessary for reading, posing the problem of increase in the loads on the IC. Since the capacitances of the capacitors are large at present, it is inevitable to use the capacitors as read capacitors. This sometimes results in narrowing the design margin. If the capacitances of the capacitors are decreased to a low level, the optimum read capacitor can be designed separately without using the capacitors. By placing this capacitor immediately before reading of IC, the loads on the IC can be decreased.
When such thin film transistors with the capacitors Cgs, Cgd are used for driving and for reading of one-dimensional or two-dimensional sensors arrayed in a matrix, these capacitors often become parasitic capacitances to cause crosstalk or the like in reading of signal and to negatively affect the operation.
Therefore, efforts have been made to eliminate the overlap widths by the so-called self-alignment (self-aligning) process for the single thin film transistor. An example thereof is shown in FIGS. 7A-7F to show schematic step diagrams for explaining an example of the production technology of self-alignment. It will be described referring to FIGS. 7A-7F.
On glass substrate 701, a first conductive layer 702 is first deposited using a material such as aluminum or chromium by vapor deposition or sputtering. Subsequently, it is patterned in a desired shape by photolithography. This is used as gate electrode 703 of thin film transistor.
Then a gate insulating film, semiconductor layers, etc. will be deposited on this gate electrode by the CVD process (Chemical Vapor Deposition) or the like. A hydrogenated amorphous silicon nitride film is first deposited as gate insulating film 704, using silane (SiH.sub.4) gas, ammonia (NH.sub.3) gas, and hydrogen (H.sub.2) gas. Subsequently, an intrinsic hydrogenated amorphous silicon layer is deposited as intrinsic semiconductor layer 705 with silane gas and hydrogen gas. Further, an N.sup.+ -type hydrogenated amorphous silicon layer is deposited as impurity semiconductor layer 706, using silane gas, and phosphine gas diluted with hydrogen gas. The technology of self-alignment is realized by improving the exposure method in photolithography upon formation of source electrode and drain electrode. Namely, photoresist 707 is formed on the N.sup.+ -type hydrogenated amorphous silicon layer 706. This photoresist is subject to back exposure from the back side of substrate, using the gate electrode 703 formed in the desired shape, as a mask. By this step the photoresist pattern 708 is formed in the same width as that of the gate electrode. After this, while keeping this photoresist pattern there, a second conductive layer 709 is deposited using the material such as aluminum or chromium by vapor deposition or sputtering. Then a stripping step of the photoresist is carried out. This causes the photoresist pattern on the gate electrode to be lifted off, whereupon the metal layer is left in the source electrode and drain electrode portions to form the source and drain electrodes. Subsequently, with the metal layer of the source electrode and drain electrode as a mask, dry etching is carried out to remove unnecessary portions of the N.sup.+ -type hydrogenated amorphous silicon layer to form the ohmic layer to the source electrode and to the drain electrode, thereby completing the source electrode and drain electrode 710, 711 having reduced overlap widths with the gate electrode.
However, since this method employs the back exposure, the second conductive layer of the light-shielding property must be formed after the exposure, and the lift-off method is unavoidable. The step of forming the source electrode and drain electrode by the lift-off takes place at the same time as stripping of the photoresist pattern on the gate electrode in the development step. In some cases cross sections of the source and drain electrodes were not always formed in self-alignment fashion (self-aligning manner) with respect to the gate electrode, contrary to expectation. There sometimes arose the problem that the step of forming the second conductive layer with the photosensitive resist kept remaining was likely to be the cause of decrease in the yield, because of development failure caused by deterioration of the photoresist by a high-temperature step (150 to 200.degree. C.).
In order to avoid the lift-off step, it is also possible to use a transparent conductive, e.g. ITO (Indium Tin Oxide), for the second conductive layer in such manner as to form the conductive material on the N.sup.+ -type hydrogenated amorphous silicon layer 706, then form a negative photoresist thereon, remove non-irradiated portions while leaving the resist only in irradiated portions, and etch the removed portions. By using the negative photoresist, the photoresist pattern except for the channel portion can be formed in the self-aligning manner with respect to the gate electrode, but, in applications of this thin film transistor for driving or for reading of one-dimensional or two-dimensional image reading apparatus in which such transistors are arrayed in a matrix, the wiring resistance is increased by the ITO wirings, which could cause difficulties in driving. Thus, it is not preferable.
In applications wherein the thin film transistors were combined with other devices, the above-stated self-aligning process had the improvable points as described above.